Originally developed by Accellera, SystemVerilog is a set of extensions to the Verilog HDL that allow for a higher level of modeling and more efficient verification of large and very large digital systems. Currently standardized as IEEE Std. 1800™-2005, the merging of both SystemVerilog and Verilog into one standard is planned for the near future. ALDEC is continuously working on improving SystemVerilog support and innovating in three areas:

• Hardware description extensions
• Assertions
• Advanced verification.

Depending on the particular Aldec tool solution and license configuration, designers can use features from different areas of the language. Riviera-PRO supports a considerable number of SystemVerilog extensions, including new data types and control structures, the interface construct and SystemVerilog assertions. While Active-HDL supports SystemVerilog design and also includes related sample designs and training materials..

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